SAFERTOS: RTOS for RISC-V
RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. Learn more about RISC-V.
Support for the RI5CY Core
RI5CY is a small 4-stage RISC-V core. It started its life as a fork of the OR10N CPU core that is based on the OpenRISC ISA.
RI5CY fully implements the RV32IMFC instruction set and many custom instruction set extensions that improve its performance for signal processing applications. It partially supports the privileged spec 1.10, USER MODE and Physical Memory Protection.
It has a custom debug support.
The core was developed as part of the PULP platform for energy-efficient computing and is currently used as the processing core for PULP and PULPino.
Support for the RV32M1 Core
The RV32M1 is an ultra-low-power, quad core solution ideal for applications that require a high performance Cortex-M4F/RI5CY processor to run the application and an efficient Cortex-M0+/ ZERO-RISCY to run radio and connectivity stack operations. Applications include portable health care devices, wearable sports and fitness devices, appliances, access control, climate control, energy management, lighting, safety and security systems.
Partners That We Work With For RISC-V Based Solutions
Free Demos & Manuals
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